Walkin Drive at Pune for HiTECH ASIC & FPGA on 27th & 28th Aug 2011
Job Description
Dear All,
We are conducting Walkin Drive at Pune for HiTECH ASIC & FPGA on 27th & 28th August 2011 ( Sat. & Sun.).
Walkin Venue : Quality inn Centurion Hotel, Shivaji Nagar, Opp. Akashwani, Pune - 411005, Tel: 020-25510600, 040-23007455, 09246372722
Walkin Time: 10.00 AM to 3.00 PM.
Job description for all positions are mentioned below
ASIC VERIFICATION : (Job Code: ASIC-V)
Experience : 2 to 10 years’ experience in the following areas:
Multiple skills required:
Expertise in System Verilog & OVM .
Expertise in System Verilog & e-specman.
Expertise in Mixed Signal Verification.
Expertise in Low Power Design Verification.
Job Location : Hyderabad & Bangalore
ASIC PHYSICAL DESIGN: ( Job Code: ASIC- PD)
Experience : 2 to 10 years’ experience in the following areas:
Partitioning,
ring preparation, Floor Planning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR drop analysis, Physical verification, Signal Integrity, Low Power design.
Job Location : Hyderabad ,Bangalore, Vizag & Noida.
ASIC IMPLEMENTATION : (Job Code: ASIC-IMP)
Experience : 2 to 10 years’ experience in the following areas:
Logic Synthesis, Low Power Synthesis, Timing Constraints, Timing Closure, Static Timing Analysis, Cross talk analysis and Repair, Formal Verification.
Job Location : Hyderabad ,Bangalore & Noida.
ASIC DFT : (Job Code: ASIC-DFT)
Experience : 2 to 10 years’ experience in the following areas:
Basic logic design, Verilog RTL and verification back ground with exposure to STA utilizing industry standard tools.
Must possess a strong knowledge of DFT including JTAG, Boundary scan, MBIST, LBIST, scan, on-chip scan compression, fault models, ATPG, and fault simulation and AC scan for at speed testing.
Expertise in industry standard EDA tools for DFT such as DFTAdvisor, fastscan/TestKompress, TetraMax, LogicVision.
Experience in Full-Chip DFT implementation of Scan, EDT/Adaptive Scan, JTAG, MBIST, Transition and Path delay ATPG.
Experience in Gate Level Simulations, Synthesis, STA and Formal Verification. Understanding of ATE and test engineering. Post-Silicon debug.
Programming in Perl, tcl, awk and c/c++.
Experience in DFT with Logic Vision tools is mandatory.
Job Location : Hyderabad ,Bangalore & Vizag .
FPGA Engineers: (Job Code: FPGA)
Experience : 2 to 10 years’ experience in the following areas
bility to interface with silicon companies and understand their requirements and expectations.
Rapidly adapt to different design and verification environments
Coordinate efforts with offshore design and verification teams
Strong experience using System Verilog & OVM / VMM
Experience in Test Benches
ACTEL based experience would be an added advantage
Job Location : Hyderabad
Qualification for all the above positions: BE/B.Tech or ME/M.Tech/MS in respective streams.
Candidates who are unable to attend the drive can forward their resumes mentioning “Job Code & Years of Experience” in the Subject line to:
Candidates have to carry relevant documents for the interview: Latest resume, academic qualification documents, Experience certificate, Latest 3 months payslips pay slips, etc.
Candidates who have attended interview with Infotech in the last 6 months are not eligible.
Best Regards,
Infotech Enterprises Ltd.
Desired Profile
Experience 3 - 8 Years
Industry Type Semiconductors/ Electronics
Role Team Lead/Tech Lead
Functional Area Embedded/EDA /VLSI/ASIC/Chip Design
Education UG - Any Graduate - Any Specialization
Keywords system verilog, e - specman, mixed signal verification, physical design, PD, floor planning, place and route,
STA, static timing, logic synthesis, low power synthesis, DFT, MBIST, LBIST, JTAG, fastscan, OVM, VMM, actel, test benches, VLSI, ASIC, FPGA
If you meet the above mentioned criteria, apply online
How To Apply- If you have not registered in Naukri.Com
Click here to Post Your FREE Resume
OR
If you have registered naukri.com,clickhere
Job Description
Dear All,
We are conducting Walkin Drive at Pune for HiTECH ASIC & FPGA on 27th & 28th August 2011 ( Sat. & Sun.).
Walkin Venue : Quality inn Centurion Hotel, Shivaji Nagar, Opp. Akashwani, Pune - 411005, Tel: 020-25510600, 040-23007455, 09246372722
Walkin Time: 10.00 AM to 3.00 PM.
Job description for all positions are mentioned below
ASIC VERIFICATION : (Job Code: ASIC-V)
Experience : 2 to 10 years’ experience in the following areas:
Multiple skills required:
Expertise in System Verilog & OVM .
Expertise in System Verilog & e-specman.
Expertise in Mixed Signal Verification.
Expertise in Low Power Design Verification.
Job Location : Hyderabad & Bangalore
ASIC PHYSICAL DESIGN: ( Job Code: ASIC- PD)
Experience : 2 to 10 years’ experience in the following areas:
Partitioning,
ring preparation, Floor Planning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR drop analysis, Physical verification, Signal Integrity, Low Power design.
Job Location : Hyderabad ,Bangalore, Vizag & Noida.
ASIC IMPLEMENTATION : (Job Code: ASIC-IMP)
Experience : 2 to 10 years’ experience in the following areas:
Logic Synthesis, Low Power Synthesis, Timing Constraints, Timing Closure, Static Timing Analysis, Cross talk analysis and Repair, Formal Verification.
Job Location : Hyderabad ,Bangalore & Noida.
ASIC DFT : (Job Code: ASIC-DFT)
Experience : 2 to 10 years’ experience in the following areas:
Basic logic design, Verilog RTL and verification back ground with exposure to STA utilizing industry standard tools.
Must possess a strong knowledge of DFT including JTAG, Boundary scan, MBIST, LBIST, scan, on-chip scan compression, fault models, ATPG, and fault simulation and AC scan for at speed testing.
Expertise in industry standard EDA tools for DFT such as DFTAdvisor, fastscan/TestKompress, TetraMax, LogicVision.
Experience in Full-Chip DFT implementation of Scan, EDT/Adaptive Scan, JTAG, MBIST, Transition and Path delay ATPG.
Experience in Gate Level Simulations, Synthesis, STA and Formal Verification. Understanding of ATE and test engineering. Post-Silicon debug.
Programming in Perl, tcl, awk and c/c++.
Experience in DFT with Logic Vision tools is mandatory.
Job Location : Hyderabad ,Bangalore & Vizag .
FPGA Engineers: (Job Code: FPGA)
Experience : 2 to 10 years’ experience in the following areas
bility to interface with silicon companies and understand their requirements and expectations.
Rapidly adapt to different design and verification environments
Coordinate efforts with offshore design and verification teams
Strong experience using System Verilog & OVM / VMM
Experience in Test Benches
ACTEL based experience would be an added advantage
Job Location : Hyderabad
Qualification for all the above positions: BE/B.Tech or ME/M.Tech/MS in respective streams.
Candidates who are unable to attend the drive can forward their resumes mentioning “Job Code & Years of Experience” in the Subject line to:
Candidates have to carry relevant documents for the interview: Latest resume, academic qualification documents, Experience certificate, Latest 3 months payslips pay slips, etc.
Candidates who have attended interview with Infotech in the last 6 months are not eligible.
Best Regards,
Infotech Enterprises Ltd.
Desired Profile
Experience 3 - 8 Years
Industry Type Semiconductors/ Electronics
Role Team Lead/Tech Lead
Functional Area Embedded/EDA /VLSI/ASIC/Chip Design
Education UG - Any Graduate - Any Specialization
Keywords system verilog, e - specman, mixed signal verification, physical design, PD, floor planning, place and route,
STA, static timing, logic synthesis, low power synthesis, DFT, MBIST, LBIST, JTAG, fastscan, OVM, VMM, actel, test benches, VLSI, ASIC, FPGA
If you meet the above mentioned criteria, apply online
How To Apply- If you have not registered in Naukri.Com
Click here to Post Your FREE Resume
OR
If you have registered naukri.com,clickhere